1. Technical Field
The invention relates broadly to semiconductor device fabrication and, more particularly, to techniques for controlling inventory of monitor wafers in an automated semiconductor factory (FAB).
2. Related Art
The following comments are adapted from an article entitled “Tracking the performance of photolithographic processes with excursion monitoring”, by Eric H. Bokclberg and Michael E. Pariseau, IBM Microelectronics.
In today's high-volume semiconductor fabs, photolithographic process steps (wafer prime, resist-apply, expose, bake, and develop) are performed in sequence hundreds of times on hundreds of wafers per day to produce well-defined photoresist patterns. In many cases, these litho process steps are combined into one tool, referred to as a photocluster, that links a resist-process track system with an exposure tool. Because lithography plays a critical role in creating device features throughout the semiconductor production operation, accurate, repeatable photocluster performance is vital, and the individual tools are typically monitored by means of numerous tool checks (inspection procedures designed to evaluate specific components of the process). Examples include resist-film-thickness and hot-plate temperature uniformity measurements on the track, and dose-uniformity and focus-control evaluations on the expose tool. Assessment of defect performance is limited to foreign material (FM) particulate inspections through subprocesses such as resist-apply, develop only, or dry-wafer handling. While the individual tool checks ensure that many of the most critical components of the litho process are within established specifications, they are unable to monitor the interactions between components, which can create out-of-spec conditions in the printed pattern even though individual tools are in spec. Consequently, the integrated litho process is also monitored through inspections and measurements of production wafers. In-line product parametric data are sorted by photocluster and displayed in tool-specific statistical process control (SPC) charts. When out-of-control trends are identified, operation of the problem tools is inhibited until the problem can be investigated and resolved.
As long as these inspections occur immediately after the litho process, and the products and levels processed on each tool are consistent from day to day (as in a large-volume, single-part-number fab), this approach to photo tool control works reasonably well. However, as fab product loading becomes more varied, with multiple part numbers and multiple levels being processed on each photo tool, trend identification becomes more difficult and individual photo tool excursions are not always immediately evident. Furthermore, when defect inspection is 1 or 2 days downstream of the photo operation and 3 days worth of data are needed to recognize a trend, thousands of wafers can be affected by a tool problem before it becomes apparent.
Detection of a tool problem in the back end of the line (BEOL) may take even longer because prior-level “noise” can obscure defects during in-line inspection, and photo process excursions may not be evident until electrical testing several weeks later. The time delays between when excursions occur and when they are actually detected are critical factors in maintaining wafer yields and device performance—for each day that a defect or dimensional problem remains undetected, hundreds of wafers can be affected.
One solution to this problem is to track each tool's defect and dimensional performance daily with an excursion monitor-a clean wafer that is processed with a unique resist pattern and then inspected for defects and critical dimensions. Because there are no influences from prior levels, the data plots for each monitor can clearly reveal problems that existed too briefly to be identified by in-line product measurements.
This article outlines the challenges faced in establishing a daily excursion monitor program and presents examples of process excursions that have been successfully identified.
The excursion monitor program that has been adopted by the IBM Microelectronics Division in Essex Junction, Vt., is a daily tool check that identifies photo-process equipment malfunctions and other process excursions as soon as they occur, minimizing product rework, scrap, and yield loss. The concept is simple: a clean wafer is fully processed through a photocluster to create a specially designed resist pattern. The monitor wafer is then inspected, defects are classified, and the resist critical dimension (CD) is measured using scanning electron microscopy (SEM). Defect and measurement data are plotted in tool-specific SPC charts to monitor each tool's performance and identify trends. Because the excursion monitor is intended to be processed, inspected, and measured in the same way that production wafers are, it has been designed for ease of manufacturability with simple, straightforward patterning that can be integrated within a normal sequence of production lots at any operation.
FIG. 1 is a diagram illustrating the excursion monitor process flow. Reclaimed wafers to be used as excursion monitors are initially inspected for FM. They are then delivered to the photocluster, where they are coated with resist and developed using a standard production resist process, except that they are exposed using a reticle specifically designed for excursion monitoring.
The aforementioned article describes the process flow of the wafer as it pertains to the use in the FAB and at the process tools.
The present invention deals with the wafer prior to entering the FAB for processing and after the wafers are selected for reclaim (last step, upper left, in FIG. 1)—namely, pre and post processing in the FAB.
A common problem with releasing monitor wafers into the FAB is staying within budget. There is also a problem with consistency in controlling the wafers while released in the FAB (releasing and getting the wafers off the floor). (“Controlling” a wafer is the process of releasing the correct part numbers to the FAB, reusing returned wafers in different process areas to reduce cost, and finally reclaiming wafers to an outside vendor. “Releasing” is the process of taking a raw wafer, placing it into a FOUP (Front Opening Universal Pod), and assigning to a wafer route so it can be used in the FAB.)